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Features
* High-performance DirectSoundTM Direct3DSoundTM Operation
- Direct Access to Audio Data as PCI Master - Uses PCI Bursts with Patented Proprietary Cache RAM to Minimize PCI Bandwidth - Mixes up to 64 Audio Channels at 48 kHz (Streaming Audio and/or Static Buffers) - Up to Eight Audio Channels in Record - Interactive Audio Includes per Channel Doppler, 4-speaker Output and Filter - Audio Effects: Reverb, Chorus, Echo, Pitch Shifting, 4-band Equalizer, Surround Top-quality Wavetable Synthesis - 16-bit Samples @ 48 kHz Sampling Rate - Up to 64-voice Polyphony by Hardware - Internal Computations on 28 Bits, DAC Support up to 22 Bits - Alternate Loop, 24 dB Digital Filter for Each Voice - Roland GSTM Format-compliant - Sample Sets under Roland(R) License, rSounds (c) Roland Corporation 1996 - DirectMusicTM Accelerator, Downloadable Sounds DLS1 Support, DLS2 Ready Multiple Audio Inputs and Outputs - AC97 Codec-compliant Interface - Three I2S Outputs (Six Audio Channels) - Four I2S inputs (Eight Audio Channels) - Home PC-ready for Dolby(R) AC-3 Six-speaker output - Dual Joystick Game Port Multi-platform - Windows(R) 95/98 Drivers - Windows(R) 2000 WDM Drivers Fully Programmable - Firmware Resides in PC Memory and in On-chip RAM - Evolutive Firmware Open to Third-party Developers Designed for PC Motherboards and Notebooks - 3.3V or 5V Operation - Choice of Standard 100-lead PQFP or Space-saving 100-lead TQFP Package
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PCI Bus Single-chip Multimedia Sound System SAM9777
* * *
Description
The highly-integrated architecture of SAM9777 is derived from the SAM9407 but contains significant improvements. The SAM9777 combines a specialized high-performance RISC-based digital signal processor (synthesis/DSP) and a general-purpose 16-bit CISC-based control processor on a single chip. A PCI interface with bus mastering capability allows the synthesis/DSP and the control processor to directly access external PC memory. A local program/data RAM, independent synthesis/DSP and control processor cache RAM, as well as PCI transfers on a PC CPU-cache line basis allow a dramatic reduction in PCI bandwidth. An intelligent peripheral I/O interface function handles other I/O interfaces such as controls received from the PCI interface in target mode, the on-chip MIDI UART, and three timers with minimum intervention from the control processor. The PCI interface also implements a legacy joystick.
Rev. 1716A-03/01
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Figure 1. Functional Overview Block Diagram
Synthesis/DSP RISC DSP Core Includes: 512 x 16 ALG RAM 128 x 28 MA1 RAM 256 x 32 MA2 RAM 256 x 32 MB RAM 128 x 16 MX RAM 256 x 16 MY RAM 64 x 13 ML RAM Codecs
DSP Cache RAM 96 x 256
PCI Interface
Initiator
Config EEPROM (optional)
P16 Processor 16-bit CISC Processor Core Includes: 256 KB x 16 Data RAM 16 x 16 Boot ROM Local Program/Data RAM 1K x 16 P16 Processor Cache RAM 20 x 256
PCI BUS
Legacy Joystick Joystick
Target I/O Functions Include: MIDI UART Timers Target FIFO MIDI
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SAM9777
SAM9777
Pin Description
PCI Bus Group
Table 1. PCI Bus Group (All signals PCI-compliant)
Pin Name AD[31:0] C/BE[3:0] PAR FRAME IRDY TRDY STOP DEVSEL IDSEL PERR REQ GNT CLK RST INTA Pin Count 32 4 1 1 1 1 1 1 1 1 1 1 1 1 1 Type I/O I/O I/O I/O I/O I/O IN I/O IN I/O TS OUT IN IN IN OD Function Multiplexed address/data Command and byte enables Parity Cycle Frame Initiator ready Target ready Indicates target requests SAM9777 to stop transaction Device select Initialization device select Parity error Request bus for master operation Master access to bus granted PCI timing clock System reset Open drain signal, interrupt request
Digital Audio Group
Table 2. Digital Audio Group
Pin Name AC_RES AC_SYNC AC_DOUT SD_OUT_0 AC_DIN SD_IN_0 BCK_OUT WS_OUT SD_OUT_1 SD_OUT_2 Pin Count 1 1 1 1 1 1 1 1 Type OUT OUT OUT IN OUT OUT OUT OUT Function AC 97 Master reset, can also be used as buffered RESET for DAC/ADC AC 97 48 kHz fixed sampling rate Multi-function pin. Configured by firmware. Serial audio stream to AC 97 or I2S data out channel 0. Multi-function pin. Configured by firmware. Serial audio stream from AC 97 or I2S data in channel 0. I2S bit clock for audio-out and master mode audio-in Multi-function pin. Output, I2S data word select for audio-out and audio-in. Multi-function pin. Output I2S auxiliary stereo-out channel #1 data @ 32 bits per sample (22 useful bits). Multi-function pin. Output I2S auxiliary stereo-out channel #2 data @ 32 bits per sample (22 useful bits).
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Table 2. Digital Audio Group (Continued)
Pin Name SD_IN_1P1 SD_IN_2P2 SD_IN_3P3 1 1 1 Pin Count Type IN or I/O IN or I/O IN or I/O Function Multi-function pin. Configuration by firmware. I2S data in channel 1 or general-purpose I/O pin. Multi-function pin. Configuration by firmware. I2S data in channel 2 or general-purpose I/O pin. Multi-function pin. Configuration by firmware. I2S data in channel 3 or general-purpose I/O pin.
Joystick, MIDI and Miscellaneous Group
Table 3. Joystick, MIDI and Miscellaneous Group
Pin Name JSX1, JSY1 JSB11, JSB12 JSX2, JSY2 JSB21, JSB22 JSREF MIDI IN MIDI OUT P0 CKIN LFT TEST0, TEST1 SCL, SDA Pin Count 2 2 2 2 1 1 1 1 1 1 1 1 Type AIN IN AIN IN AIN IN OUT I/O or OD - - IN Function Joystick 1 coordinates Joystick 1 buttons 1 & 2 Joystick 2 coordinates Joystick 2 buttons 1 & 2 Joystick reference voltage Serial MIDI-IN Serial MIDI-OUT Multi-function pin. General-purpose I/O pin 12.288 MHz master clock input (256xFs). Normally connected to AC 97 BIT_CLK PLL decoupling Test pins, should be grounded for normal operation. Optional Serial configuration EEPROM connection.
Power Supply Group
Table 4. Power Supply Group
Pin Name GND VC3 VCC AGND AVC3 Pin Count 9 9 1 1 1 Function Digital ground pins. All pins should be connected to a ground plane below the IC. 3.3V 10% digital power. All pins should be connected. 3V to 5.5V periphery power. Determines the operation level of the Codec EEPROM and MIDI signals. Analog ground for the joystick analog pins JSXn/JSYn Analog power for the joystick pins JSXn/JSYn, 3.3V 10%
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SAM9777
Pinout by Pin
Table 5. Pinout for 100-lead PQFP Package (ref. SAM9777-PQ)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name AD20 GND GND AD18 AD17 AD16 C/BE2 FRAME IRDY TRDY GND VC3 VC3 DEVSEL STOP TEST1 PERR PAR C/BE1 AD15 AD14 GND AD13 AD12 AD11 Pin Number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name AD10 AD9 VC3 VC3 AD8 C/BE0 GND AD7 AD6 AD5 AD4 AD3 VC3 AD2 AD1 AD0 SCL SDA TEST0 P0 SD_IN_1, P1 SD_IN_2, P2 SD_IN_3, P3 MIDI OUT MIDI IN Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name VCC GND GND SD_OUT_2 SD_OUT_1 WS_OUT BCK_OUT AC_RES AC_SYNC AC_DIN, SD_IN_0 CKIN AC_DOUT, SD_OUT_0 JSB22 JSB21 JSB12 JSB11 AGND JSY2 JSX2 JSREF JSY1 JSX1 AVC3 INTA LFT Pin Number 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name RST CLK VC3 VC3 GNT REQ NC GND GND AD31 AD30 AD29 AD28 AD27 VC3 AD26 AS25 AD24 C/BE3 IDSEL AD23 AD22 VC3 AD21 AD20
.
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Table 6. Pinout for Space-saving 100-lead TQFP Package (ref SAM9777-TQ)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name GND AD18 AD17 AD16 C/BE02 FRAME IRDY TRDY GND VC3 VC3 DEVSEL STOP TEST1 PERR PAR C/BE1 AD15 AD14 GND AD13 AD12 AD11 AD10 AD9 Pin Number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name VC3 VC3 AD8 C/BE0 GND AD7 AD6 AD5 AD4 AD3 VC3 AD2 AD1 AD0 SCL SDA TEST0 P0 SD_IN_1, P1 SD_IN_2, P2 SD_IN_3, P3 MIDI OUT MIDI IN VCC GND Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name GND SD_OUT_2 SD_OUT_1 WS_OUT BCK_OUT AC_RES AC_SYNC AC_DIN, SD_IN_0 CKIN AC_DOUT, SD_OUT_0 JSB22 JSB21 JSB12 JSB11 AGND JSY2 JSX2 JSREF JSY1 JSX1 AVC3 INTA LFT RST CLK Pin Number 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name VC3 VC3 GNT REQ PME GND GND AD31 AD30 AD29 AD28 AD27 VC3 AD26 AS25 AD24 C/BE3 IDSEL AD23 AD22 VC3 AD21 AD20 AD19 GND
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SAM9777
SAM9777
Mechanical Dimensions
Figure 2. 100-lead Plastic Quad Flat Pack - Rectangular
Package Dimensions (in millimeters)
Table 7. 100-lead Plastic Quad Flat Pack - Rectangular
Dimension A A1 A2 D D1 E E1 L P B 0.22 0.65 0.25 2.55 2.8 23.90 20.00 17.90 14.00 0.88 0.65 0.38 1.03 3.05 Min Typ Max 3.40
Table 8. 100-lead Thin PQFP Package - Square
Dimension A A1 A2 D D1 E E1 L P B 0.17 0.45 Min 1.40 0.05 1.35 Typ 1.50 0.10 1.40 16.00 14.00 16.00 14.00 0.60 0.65 0.22 0.27 0.75 Max 1.60 0.15 1.45
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Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings
Symbol Parameter/Condition Ambient Temperature (Power applied) Storage Temperature Voltage on any pin VCC AVC3, VC3 Note: Supply Voltage Supply Voltage Min -40 -6.5 -0.5 -0.5 -0.5 Typ Max +85 +150 VCC + 0.5 6.5 4.5 10 Unit C C V V V mA
Maximum IOL per I/O pin All voltages with respect to 0V, GND = 0V.
Recommended Operating Conditions
Table 10. Recommended Operating Conditions
Symbol VCC VC3 Note: Parameter/Condition Supply Voltage Supply Voltage
(1)
Min 3 3
Typ 3.3/5.0 3.3
Max 5.5 3.7
Unit V V C
TA Operating Ambient Temperature 0 70 1. When using 3.3V supply, care must be taken that voltage applied on pin does not exceed VCC + 0.5V.
DC Characteristics
Table 11. DC Characteristics (TA = 25C, VC3 = 3.3V 10%)
Symbol VIL VIH ICC Parameter/Condition Low-level Input Voltage High-level Input Voltage Power Supply Current Power Down Supply Current VCC 3.3 5.0 3.3 5.0 3.3 5.0 Min -0.5 -0.5 2.3 3.3 TBD TBD Typ Max 1.0 1.7 3.8 5.5 Unit V V V V mA mA A
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SAM9777
SAM9777
Functional Overview
Synthesis/DSP Engine
The synthesis/DSP engine operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 micro-instructions known as "algorithms". Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical multimedia application will use part of the capacity of the synthesis/DSP engine for fixed resource functions such as reverberation, chorus, echo, pitch-shifting, surround, equalizer, etc. The remaining capacity will typically be dynamically allocated between direct-sound play/record and wavetable synthesis. With all fixed-resource functions removed, 64-voice synthesis or 32 direct-sound channels can be achieved. Frequently-accessed synthesis/DSP parameter data are stored in five banks of on-chip RAM memory. Sample data or delay lines that are accessed relatively infrequently are stored in external PC memory and accessed through the synthesis/DSP cache RAM. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly-parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to eight simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 400 million operations per second (MOPS). Compared to the SAM9407, the synthesis/DSP engine now offers the following significant enhancements: * 24 x 16 multiplier * Direct support of 8-/16-bit mono/stereo Microsoft wave formats * No "bank" limitation * 32-bit word size for delay lines, giving virtually noise-free reverb * Pan steps of 0.75 dB * Audio data in on 20 bits * Six channels audio-out
P16 Control Processor and I/O Functions
The P16 control processor is a general-purpose 16-bit CISC processor core that runs from a local program/data RAM or from PC memory through the P16 processor cache RAM. A boot ROM is included that allows the PC to upload an initial program into the local program/data RAM at power-up. The P16 also includes 256 words of local RAM data memory. The first 16 words of this RAM hold generalpurpose registers; the next eight words hold segment and I/O registers. The remaining part of the RAM is free to store frequently-used variables and the stack. The P16 control processor writes to the parameter RAM blocks within the synthesis/DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the PCI interface and then controls the synthesis/DSP by writing into the parameter RAM banks in the DSP core. Slowly-changing synthesis functions such as LFOs are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the PCI interface through specialized "intelligent" peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16.
PCI Interface
The PCI interface can operate in both initiator and target mode. In initiator mode, the PCI interface is a PCI bus master. It can access any address in the 32-bit PC RAM space. Two base registers provide different segments for the P16 program/data and the synthesis/DSP RAM. This allows simple relocation of the synthesis/DSP address space without interrupting the P16 program. Most PCI transfers occur on a PC cache line basis, i.e., as a burst of eight 32-bit words. Such a burst will typically take 13 cycles on the PCI bus, which is about 390 ns. When playing audio at 48 kHz mono 16 bits, this means that 16 audio samples are read in 390 ns, taking only 0.12% of the PCI bandwidth. In target mode, the PCI interface is assigned I/O or memory range as defined by the plug-and-play BIOS or operating system. 16 consecutive bytes of I/O or memory space are required and a single interrupt line INTA. At power-up, the legacy devices are hidden (they do not participate in the plug-and-play enumeration). A specific
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configuration program is required to enable the legacy devices. Legacy devices are implemented in the PCI configuration registers according to Intel(R) recommendations. An optional serial EEPROM can be connected to the SAM9777. It allows the default configuration registers setting to be overridden. This allows the SAM9777 to be customized for different vendors, giving the possibility of distinguishing a SAM9777 mounted on the motherboard from a SAM9777 mounted on an audio add-in card.
Additional Information
PCI Bus Bandwidth
The PCI bus bandwidth utilized by a PCI sound card is a major concern, as it determines critical parameters such as Table 12. PCI Bus Bandwidth Instruction Execution
Functional Block 32 mono 16-bit waves @ 48 kHz, 3-D positioning Reverb with 13 delay lines Equalizer 4 bands P16 (worst case = 10% out of PC memory) Total
the number of streaming audio that can be mixed together or the maximum video frame rate for a game. Unlike most PCI sound accelerators, the SAM9777 processes everything on-chip. This includes MIDI data parsing and processing and effects like reverb, chorus, echo, equalizer, surround, filter, pitch shifting and 3-D positioning. Another unique feature of the SAM9777 device is that the built-in 16-bit processor (P16) executes instructions from a built-in local RAM and from PC memory (through a built-in cache). Thorough testing has been conducted in order to determine the PCI bus bandwidth utilization of such a structure. The results are given in Table 12 for a worst-traffic case from a typical application.
Average PCI Burst Access/Synthesis Frame 2 (read) 0.8 (read) 0.8 (write) 0 0.2 (read) 0.1 (write) 3 (read) 0.9 (write)
With: * Synthesis frame = 20833 ns * PCI burst read = 390 ns * PCI burst write = 630 ns This gives a total PCI load due to the SAM9777 of 8.3%. On this load, only 0.7% is related to the P16.
Note that this computation only takes into account the load due to the SAM9777 itself. The total load for audio depends on PC implementation (secondary cache size, DRAM configuration and speed) and on the software application implementation (wave data located in main memory or on disk). Also the load assumes that there are no retries on the PCI bus.
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SAM9777
PCI Configuration Space
The reader is assumed to be familiar with the PCI bus specification as defined in the document published by the PCI Special Interest Group PCI Local Bus Specification. Rev 2.1 June 1st, 1995.
Configuration Space Overview
Table 13. Configuration Space Overview
00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH Max_Lat = 00 - - - - - - - - - Joystick Base (default 200 - 207H) - - - - - - Min_Gnt = 00 00 00 00 00 00 00 00 00 Interrupt Pin = 01 LACR DMACFG Interrupt Line Subsystem ID = 00 00/EEP(1) 00 00 00 00 Cap_ptr = 00/EEP(1) Subsystem Vendor ID = 00 00/EEP(1) BIST = 00 Device ID = 9777/EEP(1) Status Register Class Code = 04 01 00 (Multimedia Audio) Header Type = 00 Latency Timer Vendor ID = Atmel-Dream(R) ID/EEP(1) Command Register Revision ID = 0 Cache Line = 00
Base Memory Mode Base I/O Mode 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Table 13. Configuration Space Overview (Continued)
80H 84H - -
88H 00 00 00 00 Notes: 1. EEP means that value can be replaced by EEPROM content. 2. Addresses 00H to 3FH hold the standard PCI configuration.
Configuration Registers Description PCI Standard Registers
Vendor ID (00H - 01H, read-only)
15 14 13 12 11 10 9 8a 7 6 5 4 3 2 1 0
1438H or EEPROM
Identifies the manufacturer of the device. If no EEPROM is connected, then it holds the Atmel-Dream(R) PCI ID = 1438H, otherwise it holds bytes 2 and 3 of the EEPROM. Device ID (02H - 03H, read-only)
15 14 13 12 11 10 9 8a 7 6 5 4 3 2 1 0
9777H or EEPROM
Identifies the device. It reads as 9777H if no EEPROM or bytes 4 and 5 from the EEPROM. Command (04H - 05H, partial read/write)
15 14 13 12 11 10 9 0 8a 0 7 0 6 0 5 0 4 0 3 0 2 BM 1 MS 0 IO
Reserved
Bits IO, MS, BM are read/write, all other bits are read-only and return zero. * IO: If 1, allows the device to respond to I/O space accesses (reads zero after reset). * MS: If 1, allows the device to respond to memory space accesses (reads zero after reset). * BM: If 1, allows the device to act as a master on the PCI bus (reads zero after reset). Status (06H - 07H, partial read/write)
15 DPE 14 SSE 13 RMA 12 RTA 11 STA 10 Speed 9 8a MPE 7 BTB 6 UDF 5 66M 4 3 2 Reserved 1 0
* Reserved: read-only, returns 00000 * 66M: 66 MHz-capable, read-only, returns zero * UDF: UDF supported, read-only, returns zero * BTB: Fast back-to-back capable, read-only, returns zero * MPE: Master Parity Error detected, implemented * Speed: DEVSEL timing, read-only, returns 01 (medium speed device) 12
SAM9777
SAM9777
* STA: Signaled target abort, read-only, returns 0 * RTA: Received target abort, implemented * RMA: Received master abort, implemented * SSE: Signaled system error, read-only, returns 0 * DPE: Detected Parity Error, implemented
Note: According to the PCI specification, implemented bits can only be set by device. They can be reset by writing the corresponding bit at 1.
Revision ID (08H, read-only) Indicates revision of device, returns 0 Class Code (09H - 0BH, read-only) Indicates Multimedia Audio Device, returns 04H 01H, 00H Cache Line Size (0CH, read-only) Not applicable, returns zero Latency Timer (0DH, read/write) Reads zero after reset Header Type (0EH, read-only) Returns zero (single function device) BIST (0FH, read-only) BIST not supported, returns zero Base memory mode (10H - 13H, partial read/write)
31 30 29 28 27 ... Base Address 8a 7 6 5 4 3 0 2 0 1 0 0 0
Bits 0 - 3 always read back as zero, indicating memory mode, locate anywhere in 32-bit address space, not prefetchable, size 16 bytes. Base I/O mode (14H - 17H, partial read/write)
31 30 29 28 27 ... Base Address 8a 7 6 5 4 3 0 2 0 1 0 0 1
Bits 0 - 3 always read back as 0001, indicating I/O mode, size 16 bytes. Subsystem Vendor ID (2CH - 2DH, read-only) Returns zero if no EEPROM, or bytes 6 and 7 from the EEPROM Subsystem ID (2EH - 2FH, read-only) Returns zero if no EEPROM, or bytes 8 and 9 from the EEPROM Interrupt Line (3CH, read/write) Used by the operating system to indicate interrupt routing. 13
Interrupt Pin (3DH, read-only) Returns 01H indicating that the device needs one interrupt (INTA). Min_Gnt (3EH, read-only) Minimum Grant, returns zero (no major requirement). Max_Lat (3FH, read-only) Maximum Latency, returns zero (no major requirement).
Legacy Audio Control Registers
LACR, Legacy Audio Configuration Register (40H - 41H, read/write)
15 LAD 14 13 12 11 10 9 8a 7 6 5 4 3 2 JE 1 0
The reset value of LACR is 907FH. LAD: Legacy audio disable: if 1, all legacy audio functions are disabled JE: Enable joystick function at I/O address specified by Joystick base
I/O Registers
The base address mechanism provides 16 bytes of I/O to the device. These 16 bytes can be located in memory or I/O space. Write Mode Writing a byte from base + 0 to base + 15 will send it to the P16 FIFO for further processing by the P16. Actions taken are totally firmware-dependent. Additionally, base + 2 is reserved for external EEPROM programming as follows:
7 6 5 4 3 2 1 SDA 0 SCL
SDA and SCL are write-only. Writing to these bits will be immediately reflected in the corresponding SDA and SCL pins. Read Mode Two byte registers, data and status, are implemented respectively at base + 0 and base + 1. When the P16 writes to the data register, an interrupt request is sent to the host processor. This request is cleared by the host reading the data register. The status register format is as follows:
7 Dsr* 6 Drr 5 Sx2 4 Sx1 3 Sx0 2 0 1 0 0 0
Dsr*: 0 if data pending (asserts INTA), set by read data (de-asserts INTA) Drr*: 0 if ready to accept data, 1 if P16 FIFO full Sx2, Sx1, Sx0: bits which can be programmed by the P16, indicating the type of data pending.
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SAM9777
EEPROM Format
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0EH 0FH 10H 11H - 1FH Data 55H - First byte of EEPROM identification AAH - Second byte of EEPROM identification Vendor ID low byte (Config @ 00H) Vendor ID high byte (Config @ 01H) Device ID low byte (Config @ 02H) Device ID high byte (Config @ 03H Subsystem Vendor ID low byte (Config @ 2CH) Subsystem Vendor ID high byte (Config @ 2DH) Subsystem Device ID low byte (Config @ 2EH) Subsystem Device ID high byte (Config @ 2FH) PMI Capability ID (Config @ 80H) PMI Next Item Ptr (Config @ 81H), normally zero PMI PMCSR low byte (Config @ 84H), only bits 2 to 7 used PMI PMCSR high byte (Config @ 85H), only bits 5 and 6 used PMI PMCSR_BSE (Config @ 86H), normally zero PMI Data
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Timings
All timings conditions: VCC = 5V, VC3 = 3.3V,TA = 25C The SAM9777 complies with the PCI bus and AC-97 timings. For PCI bus timings, please refer to PCI Local Bus Specification. Rev 2.1, June 1, 1995, published by the PCI Special Interest Group. For AC-97 codec timing, please refer to Audio Codec 97 Component Specification. Rev 1.03, Sept. 15, 1996, published by Audio '97 Working Group; Figure 3. Digital Audio Timing tCW WS_OUT BCK_OUT SD_OUT_x SD_IN_x tSOD tSOD tCW tCLBD Audio Codec 97, Rev 2.0, Sept. 29, 1997, published by Intel Corporation.
I2S Digital Audio
These timings refer to pins SD_OUT_0 to SD_OUT_2, SD_IN_0 to SD_IN_3, BCK_OUT, WS_OUT. tck refers to the period of the CKIN clock (typically 81.38 ns).
Table 14. Timing Parameters
Symbol tCW tSOD tCLBD Parameter BCK_OUT rising to WS_OUT change SD_OUT_x valid prior/after BCK_OUT rising BCK_OUT cycle time Min 8*tck-10 8*tck-10 16*tck Typ Max Unit ns ns ns
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SAM9777
Digital Audio Frame
Figure 4. Digital Audio Frame Format
32 periods WS_OUT
BCK_OUT
SD_OUT_x (1) SD_IN_x MSB LSB (16 bits) LSB (20 bits) LSB (18 bits) LSB (22 bits) MSB
Note:
1. SD_IN_x digital audio data is truncated to 20 bits.
EEPROM Timing
The SAM9777 complies with the Atmel AT24Cxx serial CMOS EEPROM. A low-to-high transition of RST initiates the read EEPROM by sequentially reading addresses 0 to 31 from the EEPROM and storing corresponding data into internal registers. The first two EEPROM bytes should be 55H AAH in order for the remaining 29 bytes of the loaded internal registers to be validated. The serial clock SCL for the EEPROM is derived from the PCI bus clock CLK divided by 1024 (nominal 32.2 kHz). The total read time for the EEPROM is 316 cycles (9.8 ms). The EEPROM can be written to by directly controlling the SCL and SDA data lines at I/O byte base + 2. It is the responsibility of the programmer to generate the appropriate SCL and SDA timing.
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Power-up/Reset/Power-down
The SAM9777 has a built-in PLL, allowing multiplication by 4 of an incoming clock frequency to provide the internal clock, the DSP clock and the P16 system clock. When RST is low or if no clock signal is detected on the AC 97 CKIN, then the incoming clock frequency is CLK divided by 3 (11 MHz), which is raised by the PLL at 44 MHz. When RST is high and a clock signal is detected on the AC'97 CKIN, then the incoming clock frequency is CKIN (12.288 MHz), which is raised by the PLL at 49.152 MHz. Additionally, the P16 has the possibility of entering a soft power-down mode by dividing the system clock by 32. Depending on the firmware, the P16 can decide to enter this mode by itself in case there is no audio activity or do it under control of the host processor. After a low-to-high transition of RST, the P16 starts executing instructions from a built-in bootstrap ROM. This allows the upload of an initial firmware to the P16 local program/data RAM. This firmware will communicate with the host to establish the mapping with the host memory. Firmware execution can then start from host memory.
Recommended Board Layout, LFT Filter
The pinout of the SAM9777 has been organized for direct trace connection to the PCI connector with no need for a four-layer printed circuit board. As per PCI specification, signal traces should be limited to 1.5 inches. The trace length for the PCI CLK signal should be 2.5 inches 0.1 inch. * GND, VCC, VC3 distribution, decouplings All GND, VCC, VC3 pins should be connected. GND + VC3 planes are strongly recommended below the SAM9707. The planes should be connected to all ground/+3.3V pins from the PCI connector. Recommended decoupling is 0.1 F at each corner of the IC with an additional 10 F bulk decoupling. VCC requires a single 0.1 F decoupling close to the IC. * LFT The paths between the LFT filter R-C-R and the SAM9777 should be short and shielded. The ground return from the LFT filter should be the GND plane from SAM9777. The typical LFT filter is shown in Figure 5. Figure 5. LFT Filter
LFT C2 2.2 nF R1 100
C3 10 nF GND
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SAM9777
SAM9777
Typical Design
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(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. DirectSound, Direct3DSound, DirectMusic, Windows and Microsoft are trademarks of Microsoft Corporation. Roland, Roland GS and rSounds are trademarks of Roland Corporation. Dolby is a trademark of Dolby Laboratories. Intel is a trademark of Intel Corporation. Dream is a trademark of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper.
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